1. Field of the Invention
The present invention relates generally to a power array, and more particularly, to a power array with a staggered arrangement for improving on-resistance (RDSon) and safe operating area (SOA).
2. Description of the Prior Art
Following the semiconductor industry development with time, high voltage devices have been widely applied in many electronic systems. These high voltage devices with various voltage levels are implemented as LDMOS, CMOS or DEMOS devices included in integrated circuits (IC). For example, low, intermediate and high power devices may be provided in ICs. Low power devices may be used in complementary metal oxide semiconductor (CMOS) for logic circuitry, intermediate voltage devices for analog circuitry and high power devices for high voltage output interfaces. It is desirable for high voltage devices to have a fast switching speed. The performances of such devices depend on, for example, the on resistance (RDSon) and the drain to source breakdown voltage.
For a good voltage array device, it is appreciated that the device shows good switching characteristics (ex. Low RDSon) and a widened safe operating area (SOA). Especially in the case of bigger array devices, thermal problem always impact the reliability of the device, so a widen SOA may ensure that no burn-out issue occur in the active area.
Moreover, the breakdown voltage and the on-resistance of the high voltage device are generally inversely related. There is a tradeoff between the breakdown voltage and the on-resistance. How to improve the breakdown voltage while maintaining a low on-resistance becomes a challenge.
Accordingly, a primary goal of the voltage device design is to minimize the RDSon while maintaining a high breakdown voltage and a robust SOA over the current and voltage operating area.